1. Field of the Invention
The present invention relates to a process of forming a polycrystalline silicon pattern which is used for a semiconductor device.
2. Description of the Prior Art
A polycrystalline silicon pattern is widely used as wiring and an electrode in a semiconductor device (including a gate electrode of a MOS transistor). In general, an impurity is doped in the wiring and electrode which are made of polycrystalline silicon in order to reduce the electric resistance. Especially, an electrode of polycrystalline silicon in which an impurity of high concentration is doped and which is formed to be in direct contact with an impurity region of a semiconductor substrate is also used as the diffusion source to form an impurity region. The wiring or electrode which is made of polycrystalline silicon is conventionally formed by selective etching using a photoresist mask as follows (See FIG. 1).
(1) A polycrystalline silicon layer 2 is deposited on a substrate 1 which is made of a semiconductor or insulator by the chemical vapor deposition method (CVD method). A photoresist film 3, the pattern of which is the same as a prospective pattern of the polycrystalline silicon layer 2, is formed on the polycrystalline silicon layer 2 by the Photo Engraving Process (PEP) (FIG. 1A).
(2) The polycrystalline silicon layer 2 is etched, using the photoresist film 3 as a mask, so that a desired pattern for the polycrystalline silicon layer 2 is formed (FIG. 1B).
However, the following drawbacks are presented in the conventional process. When selective etching of the polycrystalline silicon layer 2 is performed by using the photoresist film 3 as the mask, the polycrystalline silicon pattern is side-etched so that the area which is protected by the photoresist film 3 is slightly etched as shown in FIG. 1B. As a result, the patterning precision is degraded and a process for forming an elaborate semiconductor device may not be accomplished. Further, when the polycrystalline silicon pattern is used as the wiring or resistance of the semiconductor device, an impurity is doped therein to reduce the electric resistance. However, when the polycrystalline silicon layer which is doped with an impurity is etched by the process as described above, it becomes more difficult to obtain a pattern with high precision because the polycrystalline silicon which is doped with an impurity has an etching rate by plasma etching higher than the polycrystalline silicon which is not doped with an impurity. Therefore, side etching of the pattern is increased. When the wiring or resistance which is made of polycrystalline silicon is to be formed, a polycrystalline silicon layer which is not doped with an impurity is first patterned and an impurity is then ion-implanted into the entire surface of the semiconductor device. However, even if a polycrystalline silicon layer which is not doped with an impurity is used, the patterning precision is not remarkably improved, due to the side etching. Further, ions become implanted in areas other than the polycrystalline silicon pattern and these areas are damaged, thus degrading the performance characteristics of the semiconductor device. When etching is performed using a photoresist film as a mask, the polycrystalline silicon pattern may not satisfy the requirements of high precision.